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LXT381
Octal E1 Line Interface Unit
Datasheet
General Description
The LXT381 is an octal short haul analog Line Interface Unit for ITU G.703 2.048 Mbit/sec. transmission systems. It incorporates eight independent receivers and eight independent transmitters in a single LQFP-144 or PBGA-160 package. The transmit output drivers provide low impedance, constant during marks and spaces and constant pulse amplitudes independent of supply voltage variations. The LXT381 may be configured for unbalanced 75 or for balanced 120 systems without external component changes in the transmit section. The transmit return loss performance exceeds latest ETSI return loss recommendations such as ETS 300166. The LXT381 features a differential data receiver architecture with high noise interference margin. The receivers use peak detection and a variable threshold for reliable data recovery down to 500 mV or up to 12 dB of cable attenuation. Each receiver incorporates an analog Loss Of Signal (LOS) processor that meets latest ITU G.775 standard. The fast power down mode of all transmitters allows the implementation of Hitless Protection Switching (HPS) application without the use of relays.
Applications
s s s s
Synchronous Digital Hierarchy (SDH) E1 tributary interfaces
Public switching trunk line interfaces Digital Access Cross Connects (DACS) Microwave transmission systems
Product Features
s s s s s s
Octal E1 short haul line interface per ITU G.703 Single rail supply voltage of 3.3V with 5V I/O capability Low power consumption of <100 mW per channel (typ.) 75/120 TX operation without component changes Transmit return loss complies with ETSI ETS 300 166 Hitless Protection Switching (HPS)
s s s s s s s
Driver short circuit current limiter (<50 mA RMS) Differential receiver with 15dB of signal to noise interference margin Data recovery with no need for external reference clock Analog LOS detection per ITU G.775 Simple hardware control mode JTAG Boundary Scan test port per IEEE 1149.4 Small footprint 144 pin LQFP or 160 pin PBGA package
As of January 15, 2001, this document replaces the Level One document known as Octal E1 Line Interface.
Order Number: 249005-001 January 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT381 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners.
Datasheet
Octal E1 Line Interface Unit -- LXT381
Contents
1.0 2.0 Pin Assignments and Signal Descriptions......................................................5 Functional Description...........................................................................................13
2.1 2.2 2.3 2.4 2.5 Receiver ..............................................................................................................13 2.1.1 Loss Of Signal Detector .........................................................................13 Transmitter ..........................................................................................................13 2.2.1 Transmit Pulse Shaping .........................................................................14 Interfacing with 5V logic ......................................................................................14 Line Protection ....................................................................................................14 Loopbacks ...........................................................................................................14 2.5.1 Analog Loopback....................................................................................15 2.5.2 Remote Loopback ..................................................................................15 Hitless Protection Switching (HPS) .....................................................................15 Overview .............................................................................................................18 Architecture .........................................................................................................18 3.2.1 TAP Controller........................................................................................19 JTAG Register Description..................................................................................20 3.3.1 Boundary Scan Register (BSR)..............................................................21 3.3.2 Device Identification Register (IDR) .......................................................24 3.3.3 Bypass Register (BYR) ..........................................................................24 3.3.4 Analog Port Scan Register (ASR) ..........................................................24 3.3.5 Instruction Register (IR) .........................................................................25
2.6
3.0
JTAG Boundary Scan.............................................................................................18
3.1 3.2 3.3
4.0 5.0
Test Specifications ..................................................................................................27 Mechanical Specifications....................................................................................34
Datasheet
3
LXT381 -- Octal E1 Line Interface Unit
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 LXT381 144-Pin Low-Profile Quad Flat Package (LQFP) Pin Assignments and Package Markings5 LXT381 160-Pin Plastic Ball Grid Array (PBGA) Pin Assignments ....................... 6 Analog Loopback ................................................................................................ 15 Remote Looback ................................................................................................. 15 External Transmit/Receive Line Circuitry ........................................................... 17 LXT381 JTAG Architecture ................................................................................. 18 JTAG State Diagram ........................................................................................... 20 Analog Test Port Application.............................................................................. 26 Transmit Clock Timing ........................................................................................ 30 Receive Timing Diagram..................................................................................... 31 JTAG Timing ....................................................................................................... 31 E1 Mask Templates ............................................................................................ 33 LXT381 144 Pin LQFP Package Dimensions ..................................................... 34 LXT381 160 Pin PBGA Package Dimensions..................................................... 35
Tables
1 2 3 4 5 6 7 8 9 11 10 12 13 14 15 16 17 18 LXT381 Pin Description ........................................................................................ 7 Operation Mode Summary .................................................................................. 16 TAP State Description......................................................................................... 19 Boundary Scan Register (BSR) .......................................................................... 21 Device Identification Register (IDR) .................................................................... 24 Analog Port Scan Register (ASR) ....................................................................... 24 Instruction Register (IR) ...................................................................................... 26 Absolute Maximum Ratings ................................................................................ 27 Recommended Operating Conditions ................................................................. 27 Transmit Transmission Characteristics ............................................................... 28 DC Characteristics .............................................................................................. 28 Receive Transmission Characteristics ................................................................ 29 Analog Test Port Characteristics......................................................................... 30 Transmit Timing Characteristics.......................................................................... 30 Receive Timing Characteristics........................................................................... 30 JTAG Timing Characteristics .............................................................................. 31 Transformer Specifications ................................................................................. 32 G.703 2.048 Mbit/s Pulse Mask Specifications ................................................... 32
4
Datasheet
Octal E1 Line Interface -- LXT381
1.0
Pin Assignments and Signal Descriptions
Figure 1. LXT381 144-Pin Low-Profile Quad Flat Package (LQFP) Pin Assignments and Package Markings
TNEG7 RCLK7 RPOS7 RNEG7 ALOS7 RTIP7 RRING7 TVCC7 TTIP7 TRING7 TGND7 RRING6 RTIP6 TGND6 TRING6 TTIP6 TVCC6 RTIP5 RRING5 TVCC5 TTIP5 TRING5 TGND5 RRING4 RTIP4 TGND4 TRING4 TTIP4 TVCC4 RPOL OE ALOS4 RNEG4 RPOS4 RCLK4 TNEG4 TPOS7 TCLK7 ALOS6 RNEG6 RPOS6 RCLK6 TNEG6 TPOS6 TCLK6 RPD GND GND GND GND GND GND VCCIO0 GNDIO0 VCC0 GND0 LOOP0 LOOP1 LOOP2 LOOP3 LOOP4 LOOP5 LOOP6 LOOP7 TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 ALOS1 TCLK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
Part # LOT # FPO #
LXT381LE XX XXXXXX XXXXXXXX
Rev #
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TPOS4 TCLK4 ALOS5 RNEG5 RPOS5 RCLK5 TNEG5 TPOS5 TCLK5 TDI TDO TCK TMS TRST AT1 AT2 VCCIO1 GNDIO1 VCC1 GND1 GND GND GND GND GND NC NC TCLK2 TPOS2 TNEG2 RCLK2 RPOS2 RNEG2 ALOS2 TCLK3 TPOS3
Package Topside Markings Marking Part # Rev # Lot # FPO # Unique identifier for this product family. Identifies the particular silicon "stepping" -- refer to the specification update for additional stepping information. Identifies the batch. Identifies the Finish Process Order. Definition
Datasheet
TPOS0 TNEG0 RCLK0 RPOS0 RNEG0 ALOS0 GND TVCC0 TTIP0 TRING0 TGND0 RTIP0 RRING0 TGND1 TRING1 TTIP1 TVCC1 RRING1 RTIP1 TVCC2 TTIP2 TRING2 TGND2 RTIP2 RRING2 TGND3 TRING3 TTIP3 TVCC3 RRING3 RTIP3 ALOS3 RNEG3 RPOS3 RCLK3 TNEG3
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
5
LXT381 -- Octal E1 Line Interface
Figure 2. LXT381 160-Pin Plastic Ball Grid Array (PBGA) Pin Assignments
14 A B C D E F G H J K L M N P
RCLK 4 TCLK 4 RCLK 5 TCLK 5
13
RPOS 4 TPOS 4 RPOS 5 TPOS 5
12
RNEG 4 TNEG 4 RNEG 5 TNEG 5 ALOS 5
11
TVCC 4 TVCC 4 TVCC 5 TVCC 5 ALOS 4
10
TRING 4 TTIP 4 TRING 5 TTIP 5
9
TGND 4 TGND 4 TGND 5 TGND 5
8
RTIP 4
RRING 4
7
RTIP 7
RRING
6
TGND 7 TGND 7 TGND 6 TGND 6
5
TRING 7 TTIP 7 TRING 6 TTIP 6
4
TVCC 7 TVCC 7 TVCC 6 TVCC 6 ALOS 7
3
RNEG 7 TNEG 7 RNEG 6 TNEG 6 ALOS 6
2
RPOS 7 TPOS 7 RPOS 6 TPOS 6
1
RCLK 7 TCLK 7 RCLK 6 TCLK 6
A B C D E F G H J K L M N P
7 RTIP 6
RRING
RTIP 5
RRING
5
6
OE
RPOL
GND
RPD
TCK
TDO
TDI
TMS
GND
GND
GND
GND
VCCIO 1
AT 2 AT 1
TRST
GNDIO 1
GNDIO
VCC 1
GND
GND 1
LXT381BE (Bottom View)
0 GND 0
GND
LOOP 0 LOOP 2
VCCIO
0 VCC 0
LOOP 1
GND
GND
GND
GND
LOOP 3 ALOS 0 TTIP 2 TRING 2 TGND 2 TGND 2
RRING RRING
LOOP 4 ALOS 1 TNEG 1 RNEG 1
LOOP 5
LOOP 6 LOOP 7 TCLK 1 RCLK 1
N/C
N/C
ALOS 2 TNEG 2 RNEG 2
ALOS 3 TVCC 2 TVCC 2 TGND 1 TGND 1 TTIP 1 TRING 1
GND
TCLK 2 RCLK 2
TPOS 2 RPOS 2
2 RTIP 2
1 RTIP 1
TVCC 1 TVCC 1
TPOS 1 RPOS 1
TCLK 3 RCLK 3
TPOS 3 RPOS 3
TNEG 3 RNEG 3
TVCC 3 TVCC 3
TTIP 3 TRING 3
TGND 3 TGND 3
RRING
RRING
3 RTIP 3
0 RTIP 0
TGND 0 TGND 0
TTIP 0 TRING 0
TVCC 0 TVCC 0
TNEG 0 RNEG 0
TPOS 0 RPOS 0
TCLK 0 RCLK 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
6
Datasheet
Octal E1 Line Interface -- LXT381
Table 1.
Pin # LQFP 1
LXT381 Pin Description
Symbol TPOS7 I/O1 DI Transmit Positive Data Input. Transmit Clock Input. When TCLK is active, TPOS and TNEG work as NRZ inputs. TPOS and TNEG are sampled on the falling edge of TCLK. If TCLK is held High, TPOS and TNEG work as RZ inputs. In this mode, pulse widths are determined by TPOS and TNEG duty cycles. An analog timer is used to determine if TCLK is high for at least 12 seconds in order to enable the above function. If TCLK is held Low, the output drivers enter a low power high Z mode. TCLK Operating Mode Clocked NRZ H RZ L Driver Tri-State Description
Pin # PBGA B2
2
B1
TCLK7
DI
3
E3
ALOS6
DO
Analog Loss of Signal Output. Please refer to the ALOS functional description. Receive Negative Data Output. Receive Positive Data Output. These pins act as RZ data receiver outputs. The output polarity is selectable with RPOL The pins will be active High polarity when RPOL is High and Active Low Polarity when RPOL is Low. RPOS and RNEG will be active when the corresponding transceiver is in LOS. RPOS and RNEG will be in high impedance state if the RPD pin is Low. Receive Clock Output. RPOS and RNEG are internally connected to an EXOR that is fed to the RCLK output for external clock recovery applications. RCLK will be in high impedance state if the RPD pin is Low. Transmit Negative Data Input. Transmit Positive Data Input. When TCLK is active, TPOS/TNEG are active high NRZ inputs. TPOS indicates the transmission of a positive pulse whereas TNEG indicates the transmission of a negative pulse. TPOS and TNEG are sampled on the falling edge of TCLK. If TCLK is held High, TPOS and TNEG work as RZ inputs. In this mode, pulse widths are determined by TPOS and TNEG duty cycles. An analog timer is used to determine if TCLK is high for at least 12 seconds in order to enable the above function. TCLK TPOS/TNEG Operating Mode Clocked NRZ H RZ Transmit Clock Input. Receiver Power Down Input. If RPD is Low, the complete receive path is powered down and the output pins RCLK, RPOS and RNEG are switched to Tri-state mode. Ground. This pin must be connected to Ground. Ground. This pin must be connected to Ground. Ground. This pin must be connected to Ground.
4 5
C3 C2
RNEG6 RPOS6
DO DO
6
C1
RCLK6
DO
7 8
D3 D2
TNEG6 TPOS6
DI DI
9 10 11 12 13
D1 E1 E2 F1 F2
TCLK6 RPD GND GND GND
DI DI S S S
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected.
Datasheet
7
LXT381 -- Octal E1 Line Interface
Table 1.
Pin # LQFP 14 15 16 17 18 19 20
LXT381 Pin Description (Continued)
Symbol GND GND GND VCCIO0 GNDIO0 VCC0 GND0 I/O1 S S S S S S S Description Ground. This pin must be connected to Ground. Ground. This pin must be connected to Ground. Ground. This pin must be connected to Ground. Power (I/O). Ground (I/O). Power (Core). Ground (Core). Loopback Mode Select/Parallel Databus Input & Output. These pins are inputs that select the loopback mode for transceiver ports 0-7 respectively as follows:
Pin # PBGA F3 F4 G3 G1 G4 H1 H4
21 22 23 24 25 26 27 28
G2 H3 H2 J4 J3 J2 J1 K1
LOOP0 LOOP1 LOOP2 LOOP3 LOOP4 LOOP5 LOOP6 LOOP7
DI DI DI DI DI DI DI DI
Normal operation (no loopback) is selected when pin is left open (unconnected). Remote loopback mode is selected when pin is Low. In this mode, data on TPOS and TNEG is ignored and data received on RTIP and RRING is looped around and retransmitted on TTIP and TRING. Analog local loopback mode is selected when pin is High. In this mode, data received on RTIP and RRING is ignored and data transmitted on TTIP and TRING is internally looped around and routed back to the receive inputs. Note: When these inputs are left open, they stay in a high impedance state. Therefore, the layout design should not route signals with fast transitions near the LOOP pins. This practice will minimize capacitive coupling. Transmit Clock Input. Transmit Positive Data Input. Transmit Negative Data Input. Receive Clock Output. Receive Positive Data Output. Receive Negative Data Output. Analog Loss of Signal Output. Transmit Clock Input. Transmit Positive Data Input. Transmit Negative Data Input. Receive Clock Output. Receive Positive Data. Receive Negative Data. Analog Loss of Signal Output. Ground. This pin must be connected to Ground. Transmit Driver Power Supply. Power supply pin for the output driver.
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
L1 L2 L3 M1 M2 M3 K3 N1 N2 N3 P1 P2 P3 K4 K2 N4, P4
TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 ALOS1 TCLK0 TPOS0 TNEG0 RCLK0 RPOS0 RNEG0 ALOS0 GND TVCC0
DI DI DI DO DO DO DO DI DI DI DO DO DO DO S S
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected.
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Datasheet
Octal E1 Line Interface -- LXT381
Table 1.
Pin # LQFP
LXT381 Pin Description (Continued)
Symbol I/O1 Transmit Tip Output. Transmit Ring Output. Description
Pin # PBGA
45 46
N5 P5
TTIP0 TRING0
AO AO
These pins are differential line driver outputs designed to drive 75 unbalanced or 120 balanced cables with a 1:2 transformer and two 11 series resistors. TRING and TTIP will be in high impedance state if the TCLK pin is Low. Transmit Driver Ground. Ground pin for the output driver. Receive TIP Input. Receive Ring Input. These pins are the inputs to the differential line receiver. Data is recovered and output on the RPOS/RNEG pins. Transmit Driver Ground. Transmit Ring Output. Transmit Tip Output. Transmit Driver Power Supply. Power supply pin for the output driver. Receive Ring Input. Receive Tip Input. Transmit Driver Power Supply. Transmit Tip Output. Transmit Ring Output. Transmit Driver Ground. Receive TIP Input. Receive Ring Input. Transmit Driver Ground. Ground pin for the output driver. Transmit Ring. Transmit Tip Output. Transmit Driver Power Supply. Power supply pin for the output driver. Receive Ring Input. Receive Tip Input. Analog Loss of Signal Output. Receive Negative Data Output. Receive Positive Data Output. Receive Clock Output. Transmit Negative Data Input. Transmit Positive Data Input. Transmit Clock Input. Analog Loss of Signal Output. Receive Negative Data Output. Receive Positive Data Output.
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77
N6, P6 P7 N7 L6, M6 M5 L5 L4, M4 L7 M7 L11, M11 L10 M10 L9, M9 M8 L8 N9, P9 P10 N10 N11, P11 N8 P8 K11 P12 P13 P14 N12 N13 N14 K12 M12 M13
TGND0 RTIP0 RRING0 TGND1 TRING1 TTIP1 TVCC1 RRING1 RTIP1 TVCC2 TTIP2 TRING2 TGND2 RTIP2 RRING2 TGND3 TRING3 TTIP3 TVCC3 RRING3 RTIP3 ALOS3 RNEG3 RPOS3 RCLK3 TNEG3 TPOS3 TCLK3 ALOS2 RNEG2 RPOS2
S AI AI S AO AO S AI AI S AO AO S AI AI S AO AO S AI AI DO DO DO DO DI DI DI DO DO DO
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected.
Datasheet
9
LXT381 -- Octal E1 Line Interface
Table 1.
Pin # LQFP 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
LXT381 Pin Description (Continued)
Symbol RCLK2 TNEG2 TPOS2 TCLK2 NC NC GND GND GND GND GND GND1 VCC1 GNDIO1 VCCIO1 AT2 AT1 TRST I/O1 DO DI DI DI NC NC S S S S S S S S S AO AI DI Receive Clock Output. Transmit Negative Data Input. Transmit Positive Data Input. Transmit Clock Input. Not Connected. This pin must be left open for normal operation. Not Connected. This pin must be left open for normal operation. Ground. This pin must be connected to Ground. Ground. This pin must be connected to Ground. Ground. This pin must be connected to Ground. Ground. This pin must be connected to Ground. Ground. This pin must be connected to Ground. Ground (Core). Power (Core). Ground (I/O). Power (I/O). JTAG Analog Output Test Port 2. JTAG Analog Input Test Port 1. JTAG Controller Reset Input. Input is used to reset JTAG controller. TRST is pulled up internally and may be left disconnected. JTAG Test Mode Select Input. Used to control the test logic state machine. Sampled on rising edge of TCK. TMS is pulled up internally and may be left disconnected. JTAG Clock Input. Clock input for JTAG. Connect to GND when not used. JTAG Data Output. Test Data Output for JTAG. Used for reading all serial configuration and test data from internal test logic. Updated on falling edge of TCK. JTAG Data Input. Test Data input for JTAG. Used for loading serial instructions and data into internal test logic. Sampled on rising edge of TCK. TDI is pulled up internally and may be left disconnected. Transmit Clock Input. Transmit Positive Data Input. Transmit Negative Data Input. Receive Clock Output. Receive Positive Data Output. Receive Negative Data Output. Analog Loss of Signal Output. Transmit Clock Input. Description
Pin # PBGA M14 L12 L13 L14 K13 K14 J11 J12 J13 J14 H12 H11 H14 G11 G14 G13 H13 G12
96 97 98
F11 F14 F13
TMS TCK TDO
DI DI DO
99 100 101 102 103 104 105 106 107
F12 D14 D13 D12 C14 C13 C12 E12 B14
TDI TCLK5 TPOS5 TNEG5 RCLK5 RPOS5 RNEG5 ALOS5 TCLK4
DI DI DI DI DO DO DO DO DI
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected.
10
Datasheet
Octal E1 Line Interface -- LXT381
Table 1.
Pin # LQFP 108 109 110 111 112 113
LXT381 Pin Description (Continued)
Symbol TPOS4 TNEG4 RCLK4 RPOS4 RNEG4 ALOS4 I/O1 DI DI DO DO DO DO Transmit Positive Data Input. Transmit Negative Data Input. Receive Clock Output. Receive Positive Data Output. Receive Negative Data Output. Analog Loss of Signal Output. Output Driver Enable Input. If this pin is asserted Low all analog driver outputs immediately enter a high impedance mode to support redundancy applications without external mechanical relays. All other internal circuitry stays active. Receive Polarity Select Input. Determines RPOS/RNEG polarity. RPOS/RNEG are active High output polarity when RPOL is High and active Low polarity when RPOL is Low. Transmit Driver Power Supply. Power supply pin for the output driver. Transmit Tip Output. Transmit Ring Output. Transmit Driver Ground. Ground pin for the output driver. Receive Tip Input. Receive Ring Input. Transmit Driver Ground. Ground pin for the output driver. Transmit Ring Output. Transmit Tip Output. Transmit Driver Power Supply. Power supply pin for the output driver. Receive Ring Input. Receive Tip Input. Transmit Driver Power Supply. Power supply pin for the output driver. Transmit Tip Output. Transmit Ring Output. Transmit Driver Ground. Ground pin for the output driver. Receive Ring Input. Receive Tip Input. Transmit Driver Ground. Ground pins for the output driver. Transmit Tip Output. Transmit Ring Output. Transmit Driver Power Supply. Power supply pin for the output driver. Receive Ring Input. Receive Tip Input. Analog Loss of Signal Output. Description
Pin # PBGA B13 B12 A14 A13 A12 E11
114
E14
OE
DI
115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
E13 A11, B11 B10 A10 A9, B9 A8 B8 C9, D9 C10 D10 C11, D11 D8 C8 C4, D4 D5 C5 C6, D6 D7 C7 A6, B6 B5 A5 A4, B4 B7 A7 E4
RPOL TVCC4 TTIP4 TRING4 TGND4 RTIP4 RRING4 TGND5 TRING5 TTIP5 TVCC5 RRING5 RTIP5 TVCC6 TTIP6 TRING6 TGND6 RRING6 RTIP6 TGND7 TTIP7 TRING7 TVCC7 RRING7 RTIP7 ALOS7
DI S AO AO S AI AI S AO AO S AI AI S AO AO S AI AI S AO AO S AI AI DO
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected.
Datasheet
11
LXT381 -- Octal E1 Line Interface
Table 1.
Pin # LQFP 141 142 143 144
LXT381 Pin Description (Continued)
Symbol RNEG7 RPOS7 RCLK7 TNEG7 I/O1 DO DO DO DI Description Receive Negative Data Output. Receive Positive Data Output. Receive Clock Output. Transmit Negative Data Input.
Pin # PBGA A3 A2 A1 B3
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected.
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Datasheet
Octal E1 Line Interface -- LXT381
2.0
Functional Description
The LXT381 is a fully integrated octal line interface unit designed for G.703 2.048 Mbps applications. Each transceiver front end interfaces with four lines, one pair for transmit, one pair for receive. These two lines comprise a digital data loop for full duplex transmission. The LXT381 is designed to operate as an analog front-end (line driver and data recovery) without any reference clock.
2.1
Receiver
The eight receivers in the LXT381 are identical. The following paragraphs describe the operation of a single receiver. The receive signal is input to the LIU via a 1:1 transformer. See Figure 5. A peak detector samples the received signal and determines its maximum value. A percentage of the peak value is provided to the data slicers to ensure optimum signal-to-noise ratio. The receiver is capable of accurately recovering signals with up to 12dB of attenuation (from 2.37 V nominal), corresponding to a received signal level of approximately 500 mV. Regardless of received signal level, the peak detectors are held above a minimum level of 150 mV to provide immunity from impulsive noise. After processing through the data slicers, the received signal is routed to the data ports and to the receive monitor. Recovered data is output at RPOS and RNEG. RPOS/RNEG polarity is determined by the RPOL pin. In addition, RPOS and RNEG are internally connected to an EXOR that is fed to the RCLK output for external clock recovery applications. The receivers in the LXT381 can be powered down using the RPD pin. In this case, the receiver outputs RCLK/RPOS/RNEG will be in a high impedance state.
2.1.1
Loss Of Signal Detector
The LXT381 includes an analog LOS detector (ALOS pins) compliant with ITU-G.775 recommendation. The LXT381 monitors the incoming signal amplitude. Any signal below 200mV for more than 30s (typ) will assert the corresponding ALOS pin. The LOS condition is cleared when the signal amplitude rises above 250mV. The LXT381 requires more than 10 and less than 255 bit periods to declare a LOS condition in accordance to ITU G.775. During the LOS condition, the receiver outputs (RPOS and RNEG) will be held high.
2.2
Transmitter
The eight low power transmitters of the LXT381 are identical. The LXT381 transmitters can work either with NRZ or RZ formatted signals, depending on the TCLK state. See Table 2. When TCLK is active, NRZ data applied to TPOS/TNEG is clocked serially into the device. The TPOS/TNEG inputs are sampled on the falling edge of TCLK.
Datasheet
13
LXT381 -- Octal E1 Line Interface
When TCLK is held high for at least 12 s, TPOS and TNEG become RZ formatted inputs. In this mode, TPOS and TNEG control the pulse width and polarity on TTIP and TRING. If TCLK is held Low, the output drivers enter a low power, high impedance mode. The OE pin can also be used to set all the output drivers to an high impedance mode. This feature is useful for redundancy/protection applications. Each output driver is supplied by a separate power supply (TVCC and TGND).
2.2.1
Transmit Pulse Shaping
In NRZ mode, the transmitted pulse shape is internally generated using a high speed D/A converter. Shaped pulses are further applied to the line driver for transmission onto the line at TTIP and TRING. The line driver provides a constant low output impedance regardless of whether it is driving marks, spaces or if it is in transition. This well controlled dynamic impedance provides excellent return loss when used with external precision resistors ( 1% accuracy) in series with the transformer. See Figure 5. The LXT381 produces 2.048 MHz pulses for both 75 coaxial (2.37 V) or 120 shielded twisted-pair (3.0 V) lines through an output transformer with a 1:2 step up pulse transformer and 11 series resistors. No transmit component changes are required in 75 or 120 operation as the output driver dynamically adjusts its output pulse amplitude.
2.3
Interfacing with 5V logic
The LXT381 can interface with 5V logic. In this case, the VCCIO pins should be connected to a 5V power supply. The VCCIO pins feed the digital I/O pads making the input/output voltage levels consistent with 5V logic. See Table 10. The internal logic will still operate from the 3.3V supply (VCC0 and VCC1) to minimize the power consumption.
2.4
Line Protection
In the receive side, the 1 k series resistors protect the receiver against current surges coupled into the device. Due to the high receiver impedance (70 k typ.) the resistors do not affect the receiver sensitivity. In the transmit side, the Schottky diodes D1-D4 protect the output driver.While not mandatory for normal operation, these protection elements are strongly recommended to improve the design robustness.
2.5
Loopbacks
The LXT381 offers two loopback modes for diagnostic purposes. The loopback mode is selected with the LOOPn pins.
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Datasheet
Octal E1 Line Interface -- LXT381
2.5.1
Analog Loopback
When selected, the transmitter outputs (TTIP & TRING) are connected internally to the receiver inputs (RTIP & RRING) as shown in Figure 3. Data and clock are output at RCLK, RPOS & RNEG pins for the corresponding transceiver. Note: Signals on the RTIP & RRING pins are ignored during analog loopback.
2.5.2
Remote Loopback
Figure 3. Analog Loopback
TCLK TPOS TNEG
Buffer/ Pulse Shaper
TTIP TRING
RCLK RPOS RNEG
Data Recovery
RTIP RRING
During remote loopback, the RCLK, RPOS & RNEG outputs routed to the transmit circuits and output on the TTIP & TRING pins. Signals on the TCLK, TPOS & TNEG pins are ignored during remote loopback. See Figure 4. Note: because in a remote loopback, the RPOS/RNEG outputs determine the transmitter pulse width, the G.703 pulse template may not be met in this test mode. Figure 4. Remote Looback
Buffer/ Pulse Shaper
TCLK TPOS TNEG
TTIP TRING
RCLK RPOS RNEG
Data Recovery
RTIP RRING
2.6
Hitless Protection Switching (HPS)
The LXT386 transceivers include an output driver tristatability feature for T1/E1 redundancy applications. This feature greatly reduces the cost of implementing redundancy protection by eliminating external relays. Please refer to Application Note 119 for guidelines for implementing redundancy systems for both T1 and E1 operation using the LXT380/1/4/6.
Datasheet
15
LXT381 -- Octal E1 Line Interface
Table 2.
RPD L L L H H H
Operation Mode Summary
TCLK Clocked L H Clocked L H Receive Mode Power Down Power Down Power Down Data Recovery Data Recovery Data Recovery Transmit Mode NRZ Power Down1 RZ NRZ Power down1 RZ
1. In Remote loopback the driver will not power down.
16
Datasheet
Octal E1 Line Interface -- LXT381
Figure 5. External Transmit/Receive Line Circuitry
3.3V 68F 3.3V TVS1 1 0.1F
TVCC D4 RT 3 1:2
TVCC
TGND
TTIP
D3
3.3V
VCC
0.1F TVCC D2
2 560pF
Tx LINE
GND
TRING
RT D1
LXT381
(ONE CHANNEL)
1k
3 1:1 RR Rx LINE 0.22F RR
RTIP
RRING
1k
APPLICATION COMPONENT 75 COAX RT RR D1 - D4 11 1% 37.5 1% 120 TWISTED PAIR 11 1% 60 1%
INTERNATIONAL RECTIFIER 11DQ04 or 10BQ060 MOTOROLA MBR0540T1
TVS1
SGS-THOMSON SMLVT 3V3 3.3V
1 2 3
Common decoupling capacitor for all TVCC and TGND pins. Typical value. Adjust for actual board parasitics to obtain optimum return loss. Transformer turns ratio tolerance is 2%. See Test Specifications Section for transformer specifications.
Datasheet
17
LXT381 -- Octal E1 Line Interface
3.0
3.1
JTAG Boundary Scan
Overview
The LXT381 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT381 also includes analog test port capabilities. This feature provides access to the TIP and RING signals in each channel (transmit and receive.) This way, the signal path integrity across the primary winding of each coupling transformer can be tested.
3.2
Architecture
Figure 6 represents the LXT381 basic JTAG architecture. The LXT381 JTAG architecture includes a TAP Test Access Port Controller, data registers and an instruction register. The following paragraphs describe these blocks in detail.
Figure 6. LXT381 JTAG Architecture
Boundry Scan Data Register BSR Analog Port Scan Register ASR Device Identification Register IDR Bypass Register BYR Instruction Register IR
TDI
MUX
TDO
TCK TMS TRST
TAP Controller
18
Datasheet
Octal E1 Line Interface -- LXT381
3.2.1
TAP Controller
The TAP controller is a 16 state synchronous state machine controlled by the TMS input and clocked by TCK. See Figure 7. The TAP controls whether the LXT381 is in reset mode, receiving an instruction, receiving data, transmitting data or in an idle state. Table 3 describes in detail each of the states represented in Figure 7.
Table 3.
State Test logic reset Run -test/idle Capture - DR Shift - DR Update - DR Capture - IR Shift - IR Update - IR Pause - IR Pause - DR Exit1 - IR Exit1 - DR Exit2 - IR Exit2 - DR
TAP State Description
Description In this state the test logic is disabled. The device is set to normal operation mode. While in this state, the instruction register is set to the ICODE instruction. The TAP controller stays in this state as long as TMS is low. Used to perform tests. The Boundary Scan Data Register (BSR) is loaded with input pin data. Shifts the selected test data registers by one stage toward its serial output. Data is latched into the parallel output of the BSR when selected. Used to load the instruction register with a fixed instruction. Shifts the instruction register by one stage. Loads a new instruction into the instruction register. Momentarily pauses shifting of data through the data/instruction registers.
Temporary states that can be used to terminate the scanning process.
Datasheet
19
LXT381 -- Octal E1 Line Interface
Figure 7. JTAG State Diagram
1
TEST-LOGIC RESET 0
0 RUN TEST/IDLE
1
SELECT-DR 0 1
1
SELECT-IR 0 1
1
CAPTURE-DR 0 0 SHIFT-DR 1 1
CAPTURE-IR 0 0 SHIFT-IR 1 1
EXIT1-DR 0
EXIT1-IR 0
0 PAUSE-DR 1 0 0 PAUSE-IR 1
0
EXIT2-DR 1
EXIT2-IR 0
UPDATE-DR 1 0
UPDATE-IR 1 0
3.3
JTAG Register Description
The following paragraphs describe each of the registers represented in Figure 6.
20
Datasheet
Octal E1 Line Interface -- LXT381
3.3.1
Boundary Scan Register (BSR)
The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply and read test patterns to/from the board. Each pin is associated with a scan cell in the BSR register. Bidirectional pins or tristatable pins require more than one position in the register. Table 4 shows the BSR scan cells and their functions. Data into the BSR is shifted in LSB first
.
Table 4.
Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Boundary Scan Register (BSR)
I/O Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Bit Symbol PDO0 PADD0 PDO1 PADI1 PDO2 PADI2 PDO3 PADI3 PDO4 PADI4 PDO5 PADI5 PDO6 PADI6 PDO7 PADI7 PDOEN controls the LOOP0 through LOOP7 pins. N/A PDOEN Setting PDOEN to "1" configures the pins as outputs. The output value to the pin is set in PDO[0..7]. Setting PDOEN to "0" tristates all the pins. The input value to the pins can be read in PADD[0.7]. Comments
Pin Signal LOOP0 LOOP0 LOOP1 LOOP1 LOOP2 LOOP2 LOOP3 LOOP3 LOOP4 LOOP4 LOOP5 LOOP5 LOOP6 LOOP6 LOOP7 LOOP7
17 18 19 20 21 22 23 24 25 26 27
TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 N/A LOS1 TCLK0 TPOS0 TNEG0
I I I O O O O I I I
TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 HIZB1 LOS1 TCLK0 TPOS0 TNEG0 HIZB1 controls the RPOS1, RNEG1 and RCLK1 pins. Setting HIZB1 to "1" enables output on the pins. Setting HIZB1 to "0" tristates the pins.
Datasheet
21
LXT381 -- Octal E1 Line Interface
Table 4.
Bit # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
Boundary Scan Register (BSR) (Continued)
I/O Type O O O O O O O O I I I O O O O I I I I I I O O Bit Symbol RCLK0 RPOS0 RNEG0 HIZB0 LOS0 RESERVED1 LOS3 RNEG3 RPOS3 HIZB3 RCLK3 TNEG3 TPOS3 TCLK3 LOS2 RNEG2 RPOS2 HIZB2 RCLK2 TNEG2 TPOS2 TCLK2 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED8 RESERVED9 TCLK5 TPOS5 TNEG5 RCLK5 RPOS5 HIZB2 controls the RPOS2, RNEG2 and RCLK2 pins. Setting HIZB2 to "1" enables output on the pins. Setting HIZB2 to "0" tristates the pins. HIZB3 controls the RPOS3, RNEG3 and RCLK3 pins. Setting HIZB3 to "1" enables output on the pins. Setting HIZB3 to "0" tristates the pins. HIZB0 controls the RPOS0, RNEG0 and RCLK0 pins. Setting HIZB0 to "1" enables output on the pins. Setting HIZB0 to "0" tristates the pins. Comments
Pin Signal RCLK0 RPOS0 RNEG0 N/A LOS0 LOS3 RNEG3 RPOS3 N/A RCLK3 TNEG3 TPOS3 TCLK3 LOS2 RNEG2 RPOS2 N/A RCLK2 TNEG2 TPOS2 TCLK2 TCLK5 TPOS5 TNEG5 RCLK5 RPOS5
22
Datasheet
Octal E1 Line Interface -- LXT381
Table 4.
Bit # 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
Boundary Scan Register (BSR) (Continued)
I/O Type O O I I I O O O O I I O O O O I I I O O O O I I I Bit Symbol RNEG5 HIZB5 LOS5 TCLK4 TPOS4 TNEG4 RCLK4 RPOS4 RNEG4 HIZB4 LOS4 OE RPOL LOS7 RNEG7 RPOS7 HIZB7 RCLK7 TNEG7 TPOS7 TCLK7 LOS6 RNEG6 RPOS6 HIZB6 RCLK6 TNEG6 TPOS6 TCLK6 RESERVED10 RESERVED11 RESERVED12 RESERVED13 HIZB6 controls the RPOS6, RNEG6 and RCLK6 pins. Setting HIZB6 to "1" enables output on the pins. Setting HIZB6 to "0" tristates the pins. HIZB7 controls the RPOS7, RNEG7 and RCLK7 pins. Setting HIZB7 to "1" enables output on the pins. Setting HIZB7 to "0" tristates the pins. HIZB4 controls the RPOS4, RNEG4 and RCLK4 pins. Setting HIZB4 to "1" enables output on the pins. Setting HIZB4 to "0" tristates the pins. HIZB5 controls the RPOS5, RNEG5 and RCLK5 pins. Setting HIZB5 to "1" enables output on the pins. Setting HIZB5 to "0" tristates the pins. Comments
Pin Signal RNEG5 N/A LOS5 TCLK4 TPOS4 TNEG4 RCLK4 RPOS4 RNEG4 N/A LOS4 OE RPOL LOS7 RNEG7 RPOS7 N/A RCLK7 TNEG7 TPOS7 TCLK7 LOS6 RNEG6 RPOS6 N/A RCLK6 TNEG6 TPOS6 TCLK6 -
Datasheet
23
LXT381 -- Octal E1 Line Interface
Table 4.
Bit # 96 97 98
Boundary Scan Register (BSR) (Continued)
I/O Type Bit Symbol RESERVED14 RESERVED15 RESERVED16 Comments
Pin Signal -
3.3.2
Device Identification Register (IDR)
The IDR register provides access to the manufacturer number, part number and the LXT381 revision. The register is arranged per IEEE 1149.1 and is represented in Table 5. Data into the IDR is shifted in LSB first
.
Table 5.
Device Identification Register (IDR)
Bit # 31 - 28 27 - 12 11 - 1 0 Comments Revision Number Part Number Manufacturer Number Set to `1'
3.3.3
Bypass Register (BYR)
The Bypass Register is a 1 bit register that allows direct connection between the TDI input and the TDO output.
3.3.4
Analog Port Scan Register (ASR)
The ASR is a 5 bit shift register used to control the analog test port at pins AT1, AT2. When the INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects to the ASR output. After 5 TCK rising edges, a 5 bit control code is loaded into the ASR. Data into the ASR is shifted in LSB first. Table 6 shows the 16 possible control codes and the corresponding operation on the analog port. The Analog Test Port can be used to verify continuity across the coupling transformers primary winding
.
Table 6.
Analog Port Scan Register (ASR)
ASR Control Code 11111 11110 11101 11100 11011 11010 AT1 Forces Voltage To: TTIP0 TTIP1 TTIP2 TTIP3 TTIP4 TTIP5 AT2 Senses Voltage From: TRING0 TRING1 TRING2 TRING3 TRING4 TRING5
24
Datasheet
Octal E1 Line Interface -- LXT381
Table 6.
Analog Port Scan Register (ASR) (Continued)
ASR Control Code 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 AT1 Forces Voltage To: TTIP6 RTIP7 RTIP0 RTIP1 RTIP2 RTIP3 RTIP4 RTIP5 RTIP6 RTIP7 AT2 Senses Voltage From: TRING6 RRING7 RRING0 RRING1 RRING2 RRING3 RRING4 RRING5 RRING6 RRING7
The Analog Test Port can be used to verify continuity across the coupling transformer's primary winding. By applying a stimulus to the AT1 input, a known voltage will appear at AT2 for a given load. This, in effect, tests the continuity of a receive or transmit interface. See Figure 8.
3.3.5
Instruction Register (IR)
The IR is a 3 bit shift register that loads the instruction to be performed. The instructions are shifted LSB first. Table 7 shows the valid instruction codes and the corresponding instruction description.
Datasheet
25
LXT381 -- Octal E1 Line Interface
Figure 8. Analog Test Port Application
JTAG Port ASR Register
RTIP7 RRING7 TTIP7 TRING7 RTIP6 Transceiver 7
TTIP6 TRING6
1K
RTIP0 RRING0 Transceiver 0
1K
AT2 AT1
Table 7.
Instruction Register (IR)
Code # 000 010 100 110 111 Comments Connects the BSR to TDI and TDO. Input pins values are loaded into the BSR. Output pins values are loaded from the BSR. Connects the ASR to TDI and TDO. Allows voltage forcing/sensing through AT1 and AT2. Refer to Table 6. Connects the BSR to TDI and TDO. The normal path between the LXT381 logic and the I/O pins is maintained. The BSR is loaded with the signals in the I/O pins. Connects the IDR to the TDO pin. Serial data from the TDI input is passed to the TDO output through the 1 bit Bypass Register.
Instruction EXTEST INTEST_ANALOG SAMPLE / PRELOAD IDCODE BYPASS
26
Analog Mux
RRING6
Transceiver 6
Datasheet
Octal E1 Line Interface -- LXT381
4.0
Note:
Test Specifications
Table 8 through Table 18 and Figure 9 through Figure 12 represent the performance specifications of the LXT381 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in Table 10 through Table 18 are guaranteed over the recommended operating conditions specified in Table 9. Absolute Maximum Ratings
Parameter Symbol Vcc0, Vcc1, Tvcc 07 Vccio0, Vccio1, Vin Vin Vin Iin Iin
3 3
Table 8.
Min -0.5 -0.5 GND-0.5 GND-0.5 GND-0.5 2000 -10 -65
Max 4.0 7.0 VCCIO0 + 0.5 VCCIO1 + 0.5 VCC0 + 0.5 VCC1 + 0.5 100 10 100 100 +150 850 28 28
Unit V V V V V V mA mA mA mA
DC supply voltage DC supply voltage Input voltage on any digital pin Input voltage on RTIP, RRING1 ESD voltage on any Pin 2 Transient latch-up current on any pin Input current on any digital pin 3 DC input current on TTIP, TRING DC input current on RTIP, RRING Storage temperature Maximum package power dissipation Thermal resistance, junction to ambient, 144 pin LQFP package Thermal resistance, junction to ambient, 160 pin PBGA package
Iin Iin Tstor PP
C
mW
C/W C/W
Caution: Exceeding these values may cause permanent damage. Caution: Functional operation under these conditions is not implied. Caution: Exposure to maximum rating conditions for extended periods may affect device reliability. 1. Referenced to ground. 2. Human body model. 3. Constant input current.
Table 9.
Recommended Operating Conditions
Parameter Sym Vcc Vcc Ta Min. 3.135 3.135 -40 Typ. 3.3 3.3 25 Max. 3.465 5.25 +85 Unit V V Test Condition 3.3V 5%
DC supply voltage Digital I/O DC supply voltage Ambient operating temperature
C
1. Current consumption over the full operating temperature and power supply voltage range. 2. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50pF load.
Datasheet
27
LXT381 -- Octal E1 Line Interface
Table 9.
Recommended Operating Conditions (Continued)
Parameter Sym Min. Typ. ITVCC 125 100
1
Max. 265 210 100 25 -
Unit mA mA mA mA mA mA
Test Condition 100% 1's density 100% 1's density 50% 1's density 50% 1's density
Average transmitter power supply current 1
75 , coax cable 120 , TWP cable 75 , coax cable 120 , TWP cable IVCC IVCCIO Rl 40 -
Average core power supply current Average I/O power supply current Output load at TTIP and TRING
80 18 -
1, 2
1. Current consumption over the full operating temperature and power supply voltage range. 2. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50pF load.
Table 10. DC Characteristics
Parameter High level input voltage Low level input voltage High level output voltage
1
Sym VIH VIL VOH VOL VINL VINM VINH IINL IINH IIL IHZ IHZ -
Min. 2 2.4 - 1/3VCC+0.2 2/3VCC+0.2 - - -10 -10 -
Typ. -
Max. 0.8 VCCIO
Unit V V V V V V V A A A A A mA RMS A
Test Condition
IOUT= 400A IOUT= 1.6mA
Low level output voltage1 Low level input voltage Midrange level input voltage LOOP 0-7 High level input voltage Low level input current High level input current Input leakage current Tri state leakage current Tri state output current Line short circuit current Input leakage: TMS TDI TRST
- 1/2VCC - - - - -
0.4 1/3VCC-0.2 2/3VCC-0.2 50 50 +10 +10 1 50
The VCC supply refers to VCCIO0 or VCCIO1 only.
TTIP, TRING 2 x 11 series resistors and 1:2 transformer
-
-
-
50
1. Output drivers will output CMOS logic levels into CMOS loads.
Table 11. Transmit Transmission Characteristics
Parameter Output pulse amplitude Peak voltage of a space 75 120 75 120 Sym Min. 2.14 2.7 -0.237 -0.3 -1 Typ. 2.37 3.0 Max. 2.60 3.3 0.237 0.3 +1 Unit V V V V % Test Condition Tested at the line side
Transmit amplitude variation with supply 1. Guaranteed by design and other correlation methods.
28
Datasheet
Octal E1 Line Interface -- LXT381
Table 11. Transmit Transmission Characteristics (Continued)
Parameter Difference between pulse sequences Pulse width ratio of the positive and negative pulses Transmit transformer turns ratio for 75/120 characteristic impedance 51kHz to 102 kHz Transmit return loss 75 coaxial 1 Transmit return loss, 120 twisted pair cable 1 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz 51kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz Sym Min. 0.95 15 15 15 15 15 15 Typ. 1:2 17 18 17 18 19 18 0.030 0.050 Max. 200 1.05 Unit mV dB dB dB dB dB dB U.I. Test Condition For 17 consecutive pulses At the nominal half amplitude Rt = 11 1%
Using components in the LXD381 evaluation board Using components in the LXD381 evaluation board Tx path TCLK is jitter free
Transmit intrinsic jitter; 20Hz to 100kHz 1. Guaranteed by design and other correlation methods.
Table 12. Receive Transmission Characteristics
Parameter Permissible cable attenuation Receiver dynamic range Signal to noise interference margin Data decision threshold Data receiver squelch level Loss of signal threshold LOS hysteresis Receiver input impedance Input termination resistor tolerance 51 kHz - 102 kHz Input return loss1 102 - 2048 kHz 2048kHz - 3072 kHz LOS delay time LOS reset Sym DR S/I SRE Min. 0.5 -15 43 20 20 20 10 30 255 Typ. 50 150 200 50 70 Max. 12 57 1 Unit dB Vp dB % mV mV mV k % dB dB dB s marks Measured against nominal impedance @ 1.024 MHz Per G.703, O.151 @ 6 dB cable attenuation Rel. to peak input voltage Test Condition @1024 kHz
1. Guaranteed by design and other correlation methods.
Datasheet
29
LXT381 -- Octal E1 Line Interface
Table 13. Analog Test Port Characteristics
Parameter 3 dB Bandwidth Input voltage range Output voltage range Sym at13db at1iv at2ov Min. 0 0 Typ. 5 Max. VCC0 VCC1 VCC0 VCC1 Unit MHz V V Test Condition
Table 14. Transmit Timing Characteristics
Parameter Output pulse width Transmit clock frequency Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG pulse width (RZ mode) TPOS/TNEG to TCLK setup time TCLK to TPOS/TNEG hold time Delay time OE Low to driver Hi-Z Delay time TCLK Low to driver Hi-Z Sym TW TCLK TCLKT tDC tMPW TSUT THT TOEZ TTZ Min. 219 -50 10 236 20 20 8 Typ. 244 2.048 Max. 269 +50 90 252 1 15 Unit ns MHz ppm % ns ns ns NRZ mode RZ mode (TCLK = H for >16 clock cycles) Test Condition
S S
Figure 9. Transmit Clock Timing
TCLK
tSUT TPOS TNEG
tHT
Table 15. Receive Timing Characteristics
Parameter Rise/fall time
1
Sym Tr Tpwl Trxd -
Min. 20 200 -
Typ. 244 85 -
Max. 300 5
Unit ns ns ns ns
Test Condition @ CL=15 pF
RPOS/RNEG pulse width Receiver throughput delay Delay time between RPOS/RNEG and RCLK 1. For all digital outputs.
30
Datasheet
Octal E1 Line Interface -- LXT381
Figure 10. Receive Timing Diagram
RTIP
RRING
tRXD
tMPW
RPOS
tRXD tPWL
RNEG RPOL=L
Table 16. JTAG Timing Characteristics
Parameter Cycle time J-TMS/J-TDI to J-TCK rising edge time J-CLK rising to J-TMS/L-TDI hold time J-TCLK falling to J-TDO valid Sym tCYC tSUT tHT tDOD Min 200 50 50 Typ Max 50 Unit ns ns ns ns Test Conditions
Figure 11. JTAG Timing
tCYC
TCK
tSUR tHT
TMS TDI
tDOD
TDO
Datasheet
31
LXT381 -- Octal E1 Line Interface
Table 17. Transformer Specifications
Tx/Rx Turns Ratio Primary Inductance mH (min.) 1.2 1.2 Leakage Inductance H (max.) 0.60 0.60 Interwinding Capacitance pF (max.) 60 60 DCR (max.) 0.70 pri 1.20 sec 1.10 pri 1.10 sec Dielectric Breakdown Voltage V1 (min.)
TX RX
1:2 1:1
1500 Vrms 1500 Vrms
1. This parameter is application dependent.
Table 18. G.703 2.048 Mbit/s Pulse Mask Specifications
Cable Parameter TWP Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes at center of pulse Ratio of positive and negative pulse amplitudes at nominal half amplitude 120 3.0 0 0.30 244 95-105 95-105 Coax 75 2.37 0 0.237 244 95-105 95-105 Unit
V V ns % %
32
Datasheet
Octal E1 Line Interface -- LXT381
Figure 12. E1 Mask Templates
269 ns (244+25) 20%
V = 100%
10% 10%
20%
194 ns (244- 50)
NOMINAL PULSE 50%
244 ns 219 ns (244-25) 10% 10% 10% 10%
0%
20%
488 ns (244+244)
Datasheet
33
LXT381 -- Octal E1 Line Interface
5.0
Mechanical Specifications
Figure 13. LXT381 144 Pin LQFP Package Dimensions 144-Pin Low-Profile Quad Flat Package
* Part Number LXT381LE * Extended Temperature Range (-40 C to 85
D D/2
NOTE: All dimensions in millimeters.
b
E1/2
E/2 e/2
e
E1
E M
0 DEG. MIN. A2 D1/2 D1 0.08 R. MIN. A 0.25 1.00 REF. L 0 - 7 DEG. 0.08 / 0.20 R. A1
Millimeters Dimension1 A A1 A2 b D D1 E E1 e L M 0.45 0.14 Minimum 0.05 1.35 0.17 Nominal 0.10 1.40 0.22 22.00 B.S.C. 20.00 B.S.C. 22.00 B.S.C. 20.00 B.S.C. 0.50 B.S.C. 0.60 0.75 Maximum 1.60 0.15 1.45 0.27
1. See JEDEC Publication for additional specifications.
34
Datasheet
Octal E1 Line Interface -- LXT381
Figure 14. LXT381 160 Pin PBGA Package Dimensions 160-Pin Plastic Ball Grid Array
* Part Number LXT381BE * Extended Temperature Range (-40 C to 85 C)
15.00 13.00 0.20 PIN #A1 CORNER 4.72 0.10 1.00 REF 1.00 13.00
A
0.50 B 0.10 C
PIN #A1 ID 4.72 0.10
D E F
13.00 15.00 0.20 1.00
G H J K L M N P
13.0
O1.00 (3 plcs)
14 13 12 11 10 9
8
76
54
3
21
1.00 R
TOP VIEW
BOTTOM VIEW
0.85
1.61 0.19
NOTE:
1. ALL DIMENSIONS IN MILLIMETERS. 2. ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y 14.5M-1994. 3. TOLERANCE = 0.05 UNLESS SPECIFIED OTHERWISE.
SEATING PLANE
0.36 0.04
0.40 0.10
SIDE VIEW
Datasheet
35

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